The inventors incorporate IEEE Standard 802.3 in its entirety herein by reference.
1. Field of the Invention
This invention relates generally to an interface and switch for a high speed network, and more particularly to an interface and network switch capable of communicating at a nominal rate of up to 1 gigabit per second.
2. Description of the Related Art
Interconnections of and communications among computers, peripheral devices, Internet appliances (generally referred to as network clients hereinbelow) via computer networks are ubiquitous. Moreover as applications such as, multimedia, require higher data transfer rates there is a need for more robust and faster networks.
Network switches facilitate interconnections and communications among networks and network clients. Conventional networks may utilize twisted pair cable such as Category 5 and operate at a data rate of either 10 megabits per second which generally complies with IEEE Standard 802.3, section 14, commonly known as 10 BASE-T, and 100 megabits per second which generally complies with IEEE Standard 802.3, sections 24 and 25, commonly known as 100 BASE-TX, the contents of each of which are incorporated herein by reference. As the demand for increased data transfer rates is required, a newer networking standard has been proposed that utilizes twisted pair cable and operates at a nominal data transfer rate of 1 gigabit per second (1000 megabits per second). The 1 gigabit per second transfer rate complies with IEEE Standard 802.3, section 40, commonly known as 1000 BASE-T, the contents of which are incorporated herein by reference.
FIG. 1 is schematic diagram of a typical networking system. As shown therein, a computer 10 is connected to a first port of switch 20 via a communications channel, such as, twisted pair cable 30. Switch 20 may comprise 24 ports, to allow computer 10 to communicate with other computers, peripherals, network appliances and other networks.
Computer 10 comprises a media access controller or MAC 12 and physical layer interface (PHY) or transceiver 16, which are connected to each other by -an interface defined by, for example, the Media Independent Interface (MII) for 10 BASE-T standard and for 100 BASE-TX standard or the Gigabit Media Independent Interface (GMII) for 1000 BASE-T standard. MII for 10. BASE-T standard and for 100 BASE-TX standard are discussed at IEEE standard 802.3 section 22, the contents of which are incorporated herein by reference. The Gigabit Media Independent Interface (GMII) is defined by IEEE 802.3 section 35, the contents of which are incorporated herein by reference.
Media access controller 12 controls media access of transmitting and receiving packets to and from computer 10. Typically for gigabit level products, MAC 12 and PHY 16 are implemented as individual integrated circuits.
Switch 20 comprises MAC 22n and PHY 26n, which are respectively connected to each other in accordance with an interface as defined above. MAC 22n and PHY 26n are functionally similar to MAC 12 and PHY 16 of computer 10. When the network is operated in accordance with 10 BASE-T or 100 BASE-TX the interface is defined in accordance with Media Independent Interface (MII). The MII passes data to and from the MAC 22n in 4 bit wide nibbles. The nibbles are converted to and from 10BASE-T or 100BASE-TX on the network side. When the network is operated at a higher transmission rate in accordance with 1000 BASE-T, the interface is defined by the GMII. In accordance with GMII, data is passed to and from the MAC 22n in 8 bit wide bytes. The bytes are converted to and from 1000BASE-T on the network side. Note that if fiber is used on the network side then the bytes are converted to and from 1000BASE-X on the network side. In other words, the MII/GMII provides a standard interface from a MAC to a transceiver regardless of the actual protocol used on the network side.
In a system that complies with 10 BASE-T, the MII requires 16 connection lines or pins connecting the integrated circuit embodying PHY 16 and PHY 26 to integrated circuit embodying MAC 12 and MAC 22, respectively. Similarly, in a system that complies with 100 BASE-TX 16 connection lines or pins are required. In a system that complies with 1000 BASE-T 24 connection lines or pins are required. The number of pins required for MAC 12 is not a problem because there is only one MAC and one PHY. On the other hand since there are n ports in switch 20, and since the n MAC 221-22n are typically fabricated as a single integrated circuit 22, the number of pins are 24xc3x97n. For example if there are 24 ports then the n MAC 22 requires 24xc3x9724 or 576 pins. The higher number of pins result in a larger die, a larger package, a more complicated integrated circuit and higher costs, particularly at the higher data transfer rates.
Various attempts have been made to solve the above-mentioned problems. Two ad hoc standards, namely Reduced Media Independent Interface (RMII) and Serial Media Independent Interface (SMII) reduce the number of pins by serialization techniques for 10 BASE-T and 100 BASE-TX. The RMII technique requires 7 pins per port and the frequency doubles from 25 MHz to 50 MHz. Thus for a 24 port switch 7xc3x9724 or 168 pins are required. The SMII technique requires 2 pins per port plus 1 synchronizing pin and the frequency increases 5 fold from 25 MHz to 125 MHz. In this technique 2xc3x9724+1 or 49 pins are required for the SMII technique. As will be appreciated by one of ordinary skill in the art, these techniques operate at frequencies in which clock recovery between PHY 26 and MAC 22 is not required.
The GMII interface consists of 24 pins operating at 125 Megabits per second. However, design of such circuit is difficult as the length of the traces and impedances between the traces must match for good signal integrity at this higher frequency. This results in a more costly and complicated integrated circuit.
An additional requirement of a network circuit operating at 1 gigabit per second is to be backward compatible with 10 BASE-T and 100 BASE-TX networks. That is, the network circuit must detect the maximum data transmission rate capability and set the transmission rate to that rate. For example, if computer 10 is capable of a maximum transmission rate of 100 Mb per second, switch 20 having a capability of 1 gigabit per second, must detect the 100 Mb per second rate and set the transmission rate of the port of switch 20 connect to computer 10 to 100 Mb per second. This feature is commonly known as auto-negotiation. The auto-negotiation feature is typically implemented in PHY 16 and PHY 26n. PHY 16 communicates the auto-negotiated data transmission rate to MAC 12 and PHY 26n communicates the auto-negotiated data transmission rate to MAC 22n.
Traditional techniques either requires higher pin counts and complicated board routing.
Therefore, it -is an object of the present invention to overcome the aforementioned problems.
It is another object of the present invention to provide an interface between physical layer devices having data rates up to 1 gigabit per second.
It is a further object of the present invention to provide an interface between which reduces the number of pins or connections.
It is an additional object of the present invention to provide a system to efficiently control the auto-negotiated data rate.
According to one aspect of the present invention, a network device is provided which comprises a first integrated circuit having fabricated thereon a media access controller and a first serializer interface in communication with said media access controller. A second integrated circuit is provided comprising a physical layer interface in communication with an external device and a second, serializer interface in communication with physical layer interface and said first serializer interface. The first and second serializer interfaces comprise a fiber channel physical layer device implemented in accordance with 1000 BASE-X.
According to a second aspect of the present invention, the first serializer interface comprises a first receiver/decoder and a first transmitter/encoder, the second serializer interface comprises a second receiver/decoder and a second transmitter/encoder, and the first transmitter/encoder being in communication with the second receiver/decoder and the second transmitter/encoder being in communication with the first receiver/decoder.
In accordance with a third aspect of the present invention, the physical layer interface communicates with the external device at a selected one of plural data transmissions rates in accordance with a negotiated data transmission rate negotiated with the external device. The first transmitter/encoder communicates with the second receiver/decoder at a predetermined data transmission rate regardless of the negotiated transmission rate, and the second transmitter/encoder communicates with the first receiver/decoder at the predetermined data transmission rate regardless of the negotiated transmission rate.
In accordance with a fourth aspect of the present invention, the second integrated circuit further comprises a transceiver to communicate with the external device and an auto-negotiation circuit in communication with the transceiver. The auto-negotiation circuit negotiates the negotiated data transmission rate with the external device and provides a first control signal indicative of the negotiated data transmission rate to the second receiver/decoder and the second transmitter/encoder. If first control signal indicates that the negotiated data transmission rate is less than a specified data transmission rate, the second transmitter/encoder replicates data transmitted to the first receiver/decoder. The first receiver/decoder determines if any data received from the second transmitter/encoder has been replicated and provides a second control signal indicative of a received data transmission rate to the first transmitter/decoder. If the second control signal indicates that the first received data transmission rate is less than the specified data transmission rate, the first transmitter/encoder replicates data transmitted to the second receiver/decoder. The second receiver/decoder determines if any data received from the first transmitter/encoder has been replicated to determine the received data transmission rate and compares the received transmission rate with the first control signal. If the received data transmission rate is not equal to the negotiated data transmission rate, the second receiver/decoder provides a third control signal to the transceiver. The transceiver transmits idle data to the external device upon receipt of the third control signal.
In accordance with a fifth aspect of the present invention, the predetermined data transmission rate is 1.25 gigabits per second.
In accordance with a sixth aspect of the present invention, the physical, layer interface is capable of communicating with the external device at a nominal data transmission rate of 1 gigabit per second.
In accordance with a seventh aspect of the present invention, a network switch is provided and comprises a first integrated circuit having a plurality of media access controllers and a plurality of first serializer interfaces, each in communication with a respective one of the plurality of media access controllers. A plurality of second integrated circuits are provide, each comprising a physical layer interface in communication with an external device, and a second serializer interface in communication with the physical layer interface and a corresponding one the first serializer interfaces.
In accordance with a eighth aspect of the present invention the first and second serializer interfaces comprise a fiber channel physical layer device implemented in accordance with 1000 BASE-X.
In accordance with a ninth aspect-of the present invention, an integrated circuit comprises a media access controller and a serializer interface in communication with the media access controller and an external device. The serializer interface comprises a fiber channel physical layer device implemented in accordance with 1000 BASE-X.
In accordance with a tenth aspect of the present invention, an integrated circuit comprises a physical layer interface in communication with a first external device and a serializer interface in communication with the physical layer interface and a second external device. The serializer interface comprises a fiber channel physical layer device implemented in accordance with 1000 BASE-X.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.